As flash memory technologies gradually become mature, flash memories are used by increasingly more solid state drives (SSD) as basic storage units. In core components of an SSD, in addition to a flash memory, there is a controller responsible for computing and task allocation. Service data stored in the flash memory may have several bit errors after a period of time. To ensure that service data returned to an upper-layer service is accurate and valid, part of space is reserved inside the flash memory to store an error correcting code (ECC) of the service data. Each time reading the service data, the controller uses a corresponding ECC to perform error checking and correction on the data, so as to ensure as far as possible that the service data returned to the upper-layer service is accurate and valid.
As a computing capability of an SSD controller is improved and a requirement of a user on reliability and service life of an SSD becomes increasingly high, in the prior art, a popular solution is that an low density parity check code (LDPC) constructed based on a quasi-cyclic structure is used as an ECC in the SSD controller in most cases.
However, a minimum unit of internal space of the flash memory is Byte, and a code length (including an information bit and a check bit) of the LDPC based on the quasi-cyclic structure is not designed by using an integral multiple of a Byte, but designed by using an integral multiple of a magnitude of a circulant matrix. Therefore, in many cases, the code length of the LDPC constructed based on the quasi-cyclic structure cannot ideally adapt to the internal space of the flash memory.
Regarding the foregoing problem, in the prior art, the code length of the LDPC based on the quasi-cyclic structure is changed in most cases (that is, deleting or adding a check bit), to ensure that the code length ideally adapts to the internal space of the flash memory. For example, assuming that internal space of a flash memory includes data space of 4172 Bytes and redundancy check data space of 244 Bytes, and assuming that a magnitude of a quasi-circulant matrix of an LDPC based on a quasi-cyclic structure is 128 bits, a code length of the LDPC based on the quasi-cyclic structure is an integral multiple of 128 bits. It can be learnt from the foregoing example that neither the data space of 4172 Bytes nor the redundancy check data space of 244 Bytes is an integral multiple of 128 bits. Therefore, the foregoing code length of the LDPC based on the quasi-cyclic structure cannot ideally adapt to the internal space of the flash memory. In the prior art, a manner in which the code length of the LDPC based on the quasi-cyclic structure is changed by deleting a check bit is specifically as follows: A puncturing operation is performed on check bits of the LDPC based on the quasi-cyclic structure. That is, round-up is performed on 244×8/128=15.25 to obtain 16, the designed check bits of the LDPC based on the quasi-cyclic structure is 16×128/8=256 Bytes, and redundant 12 Bytes are deleted by means of the puncturing operation and are not stored in the actual redundancy check data space of the flash memory. However, original check bits of the LDPC based on the quasi-cyclic structure are changed due to the puncturing operation, and consequently, an error correction capability is degraded, or even an error floor phenomenon that cannot be corrected occurs, and finally, the reliability and the service life of the SSD are affected. Similarly, changing the code length of the LDPC based on the quasi-cyclic structure by adding a check bit also causes a change of the original check bits of the LDPC based on the quasi-cyclic structure and causes degrading of the error correction capability, and finally, the reliability and the service life of the SSD are affected.
In conclusion, although the manner in the prior art in which the code length of the LDPC based on the quasi-cyclic structure is changed (that is, deleting or adding a check bit) can ensure that the code length ideally adapts to the internal space of the flash memory, the error correction capability of the LDPC based on the quasi-cyclic structure is degraded, and finally, the reliability and the service life of the SSD are affected.